The present invention generally relates to charge coupled devices and methods of producing the same, and more particularly to a charge coupled device having an ion implanted region and a method of producing such a charge coupled device.
Recently, the integration density of charge coupled device (CCD) area sensors has been improved. For example, a CCD having 250,000 pixels for an 1/3 inch area is used for a video camera for home use, and video cameras for business (or professional) use are becoming smaller using a CCD having a large number of pixels. A CCD having 2,000,000 pixels is being developed for high definition televisions which are anticipated as media of the next generation. Therefore, there are demands to further reduce the size and further increase the number of pixels of the CCD, and in order to satisfy such demands, it is necessary to improve the integration density of the CCD channel part and ensure a sufficient charge transfer quantity.
The CCD transfers the charge which is stored in a potential well within a substrate, along the field. For example, the following steps are taken when forming a buried channel type CCD.
First, as shown in FIG. 1A, a p-type well 102 is formed in a silicon (Si) substrate 101, and an n-type impurity such as arsenic (As) and phosphor (P) is implanted into the p-type well 102 to make it active, that is, to form an n-type layer 103 having a uniform depth at the upper or surface part of the p-type well 102.
Next, as shown in FIG. 1B, A silicon dioxide (SiO.sub.2) layer 104 and a polysilicon layer are successively formed on the n-type layer 103, and the polysilicon layer is patterned into a stripe pattern, for example, using a photolithography method. Each stripe of the patterned polysilicon layer is used as a first gate electrode 105.
Thereafter, the exposed portions of the SiO.sub.2 layer 104 at the opposite sides of each gate electrode 105 are removed by etching, and a SiO.sub.2 layer 107 is formed on the entire top surface of the stacked structure as shown in FIG. 1C. This SiO.sub.2 layer 107 is used as an interlayer insulator.
Next, the gate electrode 105 is used as a mask to implant a p-type impurity such as boron (B) into the p-type well 102 and an annealing step is performed to make the impurity region active. As a result, an n.sup.- -type diffusion layer 106 is formed in a region of the p-type well 102 between two adjacent first gate electrodes 105, as shown in FIG. 1C.
Finally, a second gate electrode 108 is formed on the interlayer insulator (SiO.sub.2 layer) 107 between two adjacent first gate electrodes 105.
In this case, the gate length of the first gate electrode 105 is set greater than that of the second gate electrode 108. The n-type layer 103 under the first gate electrode 105 is used as a charge storage region, and the n.sup.- -type diffusion layer 106 under the second gate electrode 108 is used as a barrier region.
Adjacent first and second gate electrodes 105 and 108 form a pair, and a 2-phase voltage, for example, is applied to the gate electrodes 105 and 108 of the adjacent pair so as to form a potential well under the gate electrodes 105 and 108. The charge is trapped and transferred using this potential well.
Although attempts have been made to reduce the size of the CCD, it is necessary to increase the quantity of charge which is transferred in order to maintain the same characteristic. In addition, the length of the n-type layer 103 under the first gate electrode 105 used as the charge storage region must be made as large as possible.
However, according to the conventional steps described above, B ions are implanted when forming the n.sup.- -type diffusion layer 106, and this layer is made active by a thermal process. For this reason, the implanted B ions diffuse horizontally and narrow the n-type layer 103 which forms the charge storage region, and there is are problems in that the quantity of charge which can be transferred becomes small and the signal-to-noise (S/N) ratio becomes poor.